The present invention relates to an adder cell for a ripple-carry adder and more particularly to such a cell which may be executed in CMOS technology as an integrated circuit.
Adders are required in a large number of digital logic circuits, for example in digital filters, signal processors, and microprocessors. A principle for such an adder is the ripple-carry method, in which a carry signal is serially transmitted from an adder cell for a lower-order bit to the adder cell for the next higher order bit. The addition time is defined essentially by the time required for the carry propagation. More involved adder arrangements such as, for example, the look-ahead carry method are based on the ripple-carry method.
Ripple-carry adder cells are known, for example, from H. Weiss, K. Horninger, "Intergrierte MOS-Schaltungen", Springer-Verlag, Berlin-Heidelberg, New York (1982), pp. 188-194. Such adders cells are affected by the disadvantage that the carry path, which is a critical determinant of overall computing time of an arithmetic unit constructed with such cells, either has a relatively large number of serially connected gates, or else the gates are components of combination gates. In the former case, the large number of serially connected gates has an unfavorable effect on the propagation time of carry signals. In the second case, there may be the additionally unfavorable fact that the charging of the capacitance of the carry output does not take place with the required edge steepness, due to the relatively high impedance of the gates fashioned as component parts of combination gates.